The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...
It digitizes into 16 bit words the low level signals generated by a transducer, thanks to a programmable gain amplifier, an analog sigma-delta modulator and a digital low-pass filter. The aim of this ...
The company provides data converter products, which translate real-world analog signals into digital data, as well as translates digital data into analog signals; power management and reference ...