Design-Reuse1mon
SMIC Clock Generator PLL IP Core
This IP is a programmable Analog PLL suitable for high speed clock generation. The high speed VCO can run from 800MHz to 3200MHz.By setting DM [5:0] and DN [11:0] to different values according ... The ...
Design-Reuse5d
Analog & Mixed Signal IP Core
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock ...